In general, processes such as a film-forming process and a pattern etching process are repeatedly performed to manufacture semiconductor devices. In this regard, the line width and hole diameter become gradually reduced in response to the demand for higher integration and higher miniaturization of the semiconductor devices. Since it is required to reduce the electric resistance further due to the scaling-down of various dimensions, an inexpensive copper having a small electric resistance tends to be used as a wiring material or a filling material for filling a recessed portion such as a trench, a hole or the like (see, e.g., Japanese Patent Application Publication No. 2004-107747). As such, in case that the copper is used as a wiring material or a filling material, a tantalum (Ta) film, a tantalum nitride (TaN) film or the like is typically used as a barrier layer in consideration of its barrier property against the diffusion of copper to an underlying layer thereof.
In order to fill a recessed portion with the copper, a thin seeding film formed of a copper film is first formed on the entire surface of a wafer including the entire wall surface of the recessed portion. Then, the recessed portion is completely filled by plating the entire surface of the wafer with the copper. Thereafter, remnants of the copper thin film are removed from the surface of the wafer by a chemical mechanical polishing (CMP).
Such a process will be described with reference to FIGS. 14A to 14C. FIGS. 14A to 14C are views for explaining a conventional filling process on a recessed portion of a semiconductor wafer.
A recessed portion 2, e.g., a through hole, a groove (trench), a via hole for forming a dual damascene pattern, or the like, is formed on a surface of an insulation layer 1, e.g., an interlayer dielectric film, formed on a semiconductor wafer W. On the bottom of the recessed portion 2, a lower wiring layer 3 formed of, e.g., a copper is formed to be exposed.
Specifically, the recessed portion 2 includes an elongated groove (trench) 2A having a concave section; and a hole 2B formed at a part of the bottom portion of the recessed portion 2. The hole 2B becomes a contact hole or a through hole. The wiring layer 3 is exposed on the bottom of the hole 2B to make an electric connection to a lower wiring layer (not shown), a transistor (not shown) and/or the like.
The insulation layer 1 is formed of, e.g., a film mainly containing SiO2. In response to the scaling-down of the design rule, the width of the recessed portion 2 is formed to be very small, e.g., about 120 nm, and the aspect ratio thereof is set to range from, e.g., about 2 to 4. The shape shown in FIGS. 14A to 14c is simplified by omitting the illustration of a diffusion barrier film, an etching stop film and the like.
On the surface of the semiconductor wafer W including the inner surface of the recessed portion 2, a barrier layer 4 made of, e.g., a TaN film and a Ta film is substantially uniformly pre-formed by using a plasma sputter device (see FIG. 14A). Then, by the plasma sputter device, a seeding film 6 formed of a thin metal film, e.g., a copper film, is formed over the entire surface of the wafer including the inner surface of the recessed portion 2 (see FIG. 14B). When the seeding film 6 is formed in the plasma sputter device, an RF bias power is supplied to the semiconductor wafer and, thus, the attraction of copper ions thereto is efficiently performed. Further, by performing a copper plating process on the surface of the wafer, the inside of the recessed portion 2 is filled with a metal film 8 formed of, e.g., a copper film (see FIG. 14C). Thereafter, remnants of the metal film 8, the seeding film 6 and the barrier layer 4 are polished by the CMP or the like to be removed.
Recently, various developments have been made to further improve the reliability of the barrier layer. Especially, the attention is given to a self-forming barrier layer using a manganese (Mn) film or the like instead of the Ta film or the TaN film (see, e.g., Japanese Patent Applications Publication Nos. 2005-277390 and 2007-067107). The Mn film is formed by the sputtering, and the Mn film itself serves as a seeding film. Accordingly, a Cu plating layer is directly formed thereon.
By performing an annealing process after the plating, the Mn film reacts with a SiO2 film serving as the lower insulation film by self-alignment, so that an Mn barrier film such as MnSixOy film (x and y being positive numbers (the same hereinafter)) or a manganese oxide MnOx (x being a positive number) at a boundary portion of the SiO2 film and the Mn film. In this way, it is possible to reduce the number of the manufacturing processes.
In this regard, in the case of a thin Mn film, an entire part of the film is formed of MnOx or MnSixOy. Further, the manganese oxide includes MnO, Mn3O4, MnO2 and the like depending on the valency of the Mn, which are generally referred to as “MnOx.”
In the meantime, the Mn barrier film has a relatively good barrier property against the Cu film, while the Cu film formed on the Mn film or the Mn barrier film has a relatively poor wetting property (wettability). As a result, since the adhesivity of the Cu film formed on the Mn film or the Mn barrier film becomes poor, the adhesive inferiority may occur between the Cu film and the Mn film or the Mn barrier film.